For purposes of fully explaining the current technical levels regarding the present invention, the patents, patent applications, patent publications, scientific literatures and etc. that are referenced or specified are all incorporated herein by reference
Due to the progress in the semiconductor technology, the degree of integration of semiconductor devices (logical LSIs [Large Scale Integrated circuits]) has been increasing year by year, thus making it possible to integrate a large-scale system into one chip. However, since semiconductor devices are very costly and take a long time to manufacture, it is critical to perform adequate verification thereof prior to manufacturing.
Verification of semiconductor devices is performed at a variety of design phases. Design processes include a number of stages from an abstract level at an initial design to a detailed manufacturing level at a final stage, and handle logical information depending on each level. For example, at an initial design phase, logical information of an abstract level which defines relationships between inputs and outputs; at a functional design stage, logical information of a functional level which defines functions of each logical section; and a final detailed design stage, logical information of a structural level which defines a logical structure, are each handled. Logical information of the aforementioned variety of design stages can be expressed in various hardware descriptive languages (SystemC, SystemVerilog, Verilog-HDL, VHL etc.) which are commonly used.
A method of logical verification of a semiconductor device or a system using semiconductor devices includes those that use a software simulator, a hardware simulator and an actual semiconductor device. The software simulator can be used at a variety of design stages because it executes logical information described in hardware descriptive language as computer programs. The software simulator also has the advantage that values of all variables in a hardware descriptive language can be readily observed because it executes operations of circuits as computer programs.
On the other hand, actual semiconductor devices and hardware emulators can execute logical operations at higher speeds than the software emulator because they are hardware. In general, the hardware emulator is a device constituted by a rewritable hardware (programmable logic device), such as FPGA (Field Programmable Gate Array), FPID (Field Programmable Interconnect Device) etc. However, general semiconductor devices and hardware simulators are problematic in that, since they are unable to observe all signals for reasons of cost, hardware constraints and etc., it is difficult for them to debug circuits.
In order to overcome the above-mentioned problem, Patent Documents 1 and 2 disclose an approach to read values of memory elements implemented in any FPGA without support of spatial hardware, by controlling the function of a lead back capture possessed by FPGA through JTAG (Joint Test Action Group) (IEEE1149.1) which is a standard for a boundary scan test, a test accessory support, etc. This approach significantly alleviates the observation problem associated with the hardware simulator described above.